In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was dealt with, overall strengths and weaknesses of a design approach, etc. This information can be used to make decisions regarding market positioning, future designs and new product development. The information resulting from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis and other technical means. At the core of this activity is the process of design analysis which, in this context, refers to the techniques and methodology of deriving complete or partial schematics, starting with essentially any type of integrated circuit in any process technology. For such technical information to be of strategic value it must be accurate and cost-effective, and it is very important that the information should be timely.
A design analysis process typically involves skilled engineers manually extracting circuit information from a set of large "photomosaics" of an integrated circuit (IC). Skilled technicians and engineers perform the following sequential manual tasks:
(1) Capture Image: PA0 (2) step (i) is repeated for all of various regions of interest of the layer of the IC, ensuring that sufficient overlap exists between adjacent photographs that will be used to create photomosaics. PA0 (3) Create Photomosaics: PA0 (4) steps (1)-(3) are repeated for all layers (l)-(N) necessary to construct a layout database of the IC. All layers include interconnect layers. For example, four sets of photomosaics are required for a state-of-the-art microprocessor employing four layers of interconnect: three layers of metal and one layer of polysilicon. PA0 (5) Extract Circuit: PA0 (6) Organize Schematic: PA0 (7) Capture Schematic: PA0 1. Segmentation and polygon generation results are degraded around the boundaries of each of the images, which increased the amount of operator interaction. This could be minimized, by decreasing the perimeter to area ratio of the size of each image being captured. This minimizes the problem without solving the source PA0 2. Registering of polygon data is not as precise as registering of images. Although a saving is generated in terms of computing time, operator time, especially at the vertical alignment phase, is increased. PA0 3. Vertical alignment employes a potentially large search to align the different IC layers to each other. This search involves aligning sets of contacts and vias to each other from successive layers. This task could be hampered by a number of reasons: PA0 4. No facility for correcting `beam twist` in an SEM-like system is provided.
(i) a high magnification photograph is taken, using a camera, of a small portion of an IC which has been processed to expose a layer of interest. PA1 (ii) all adjacent photographs associated with the given IC layer are aligned and taped together. PA1 (iii) transistors, logic gates and other elements employed in the IC are identified by manually visually examining the polysilicon and lower metal interconnect photomosaics. PA1 (iv) interconnections between circuit elements of (iii) are traced and this information is captured in the form of schematic drawings. PA1 (v) drawings of (iv) are manually checked against the photomosaics and any obvious errors are corrected. PA1 (vi) the drawings of (v) are organized into hierarchial functional/logical blocks. PA1 (vii) the drawings of (vi) are entered into a computer using computer aided engineering (CAE) software tools for subsequent simulation and functional analysis of the IC. PA1 i. If deprocessing was poor, contacts/vias would not necessarily be easily replicated from layer-to-layer. Contacts/vias from successive layers may not necessarily be available. PA1 ii. The preferred embodiment of that invention used an SEM to perform image capture. Any SEM magnification drift could not be accommodated in the previous disclosure. PA1 iii. The search for a match could potentially be quite time consuming since no previous knowledge of a cross-reference point was available. Additionally, due to the often repetitive nature of integrated circuits, there was a chance of aligning the layers at the wrong location. If the `layer misalignment` threshold was set too low, no match may be found.
Fully manual techniques for circuit extraction are not reliable since the task of extracting circuit information can be quite arduous and is prone to errors. Surprisingly, researchers have explored automated circuit extraction procedures instead of computer-assisted techniques. Because of the image processing techniques used to extract circuit information, the device must have excellent clarity on all the IC layers (i.e. no residuals from previous layers, and no stripping of the current layer). This is a heavy burden for the chemical etches used to prepare the samples (remove oxide, strip off IC layers, clean the sample, etc . . . )
Some systems have attempted to be fully automated, but no system has been designed to `aid` the engineer in extracting the device and interconnect information. The prior art generally involves some sort of image processing or pattern recognition to identify the polygons which constitute the layout. Such systems are described in U.S. Pat. No. 5,086,477 issued Feb. 4, 1992 to Kenneth K Yu et al and U.S. Pat. No. 5,191,213 issued Mar. 2, 1993 to Haroon Ahmed et al. and also U.S. patent application Ser. No. 08/420,682.
In the system described in U.S. Pat. No. 5,086,477, the integrated circuit chip is scanned by a microscope or scanning electron microscope (SEM). The system identifies every unique cell and/or gate used in the integrated circuit. A unique abstract representation is created for each of these unique cells or gates, which are stored in a library.
However, without any operator guidance, the system cannot know where the boundary of a cell lies. While the patent suggests the use of diffusion edges to define cell boundaries, it appears that the only way that this can be done is by manual operator direction.
In the patented system, once all unique cells have been captured in a reference library. the system attempts to associate and match all abstract features contained in the layout data base to the cells in the reference library using classical template matching. However because of the magnitude of data contained in a layout data base for a typical modem integrated circuit, even after the data has been compressed, the processing time required to reliably extract a netlist is large. The difficulty and time required for the operator directed process becomes very difficult with a large number of cells or gates, since the number of template matching operations increases exponentially with the number of reference cells and/or gates.
Once all reference cells in the patented system have been template matched to the data base, theoretically all features in the layout data base will have been grouped and classified and a netlist can be constructed. If all the features of the layout data base have been classified then a netlist can be constructed. If there are features of the layout data base that have not been classified, either the system must construct a new cell or gate to be added to the reference library and an operator is informed, or the operator is informed by the system and the operator performs this task. The cell to cell interconnect information extraction, which is required to construct a netlist, is said to be performed using template matching, which is very inefficient.
Due to the template matching approach that is required, the patented system should be limited to gate-array or very structured standard cell integrated circuit analysis in which the large majority of the cells are identical, since as the number of cells in the integrated circuits increase, the efficiency decreases. It is therefore inefficient for analysis of modern ASICs or custom integrated circuits, large and/or complex integrated circuits. The patented system would also be limited to applications where many devices from a few ASIC manufacturers are investigated, due to the investment and time required to develop separate reference libraries, e.g. related to a different set of design rules.
U.S. Pat. No. 5,191,213 relates to a technique for removing layers of an integrated circuit and for scanning each of the layers.
U.S. Pat. No. 5,694,481 discloses a system which performs the following steps, in the following order: a) image capture; b) image segmentation and polygon generation; c) registering (of polygon data); d) vertical alignment; e) schematic generation. Although an improvement over the prior art this technique still has its limitations, some of them being:
None of the previous techniques has the structure and advantages of the method included in the present invention.